An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform

Shrutisagar Chandrasekaran, Abbes Amira, Shi Minghua, Amine Bermak

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

In this paper, an efficient architecture for the Finite Ridgelet Transform (FRIT) suitable for VLSI implementation based on a parallel, systolic Finite Radon Transform (FRAT) and a Haar Discrete Wavelet Transform (DWT) sub-block, respectively is presented. The FRAT sub-block is a novel parametrisable, scalable and high performance core with a time complexity of O(p 2), where p is the block size. Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) implementations are carried out to analyse the performance of the FRIT core developed.

Original languageEnglish
Pages (from-to)183-193
Number of pages11
JournalJournal of Real-Time Image Processing
Volume3
Issue number3
DOIs
Publication statusPublished - Sep 2008
Externally publishedYes

Fingerprint

Field programmable gate arrays (FPGA)
Mathematical transformations
Radon
Discrete wavelet transforms
Application specific integrated circuits

Keywords

  • ASIC
  • Finite Radon Transform
  • Finite Ridgelet Transform
  • FPGA
  • Image processing
  • VLSI
  • Wavelets

ASJC Scopus subject areas

  • Information Systems

Cite this

An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform. / Chandrasekaran, Shrutisagar; Amira, Abbes; Minghua, Shi; Bermak, Amine.

In: Journal of Real-Time Image Processing, Vol. 3, No. 3, 09.2008, p. 183-193.

Research output: Contribution to journalArticle

Chandrasekaran, Shrutisagar ; Amira, Abbes ; Minghua, Shi ; Bermak, Amine. / An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform. In: Journal of Real-Time Image Processing. 2008 ; Vol. 3, No. 3. pp. 183-193.
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