A VLSI architecture for a run-time multi-precision reconfigurable booth multiplier

Zhou Shun, Oliver A. Pfänder, Hans Jörg Pfleiderer, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

In this paper, a reconfigurable multi-precision Radix-4 Booth multiplier structure is presented. The reconfig-urable 8 × 8 bit multiplier unit can be cascaded to form a multiplier that can adapt to variable input precision requirements. The number of bits can be extended by concatenating more stages together. For example, four 8 × 8 bit units can be used to build a 16 × 16 bit Booth multiplier. In our proposed architecture, the multiplier adapts to different bit-lengths by using external control signals. The performance of our reconfigurable multiplier are compared with a parallel array multiplier and a conventional Booth multiplier. The comparison is based on synthesis results obtained by synthesizing all multiplier architectures targeting a Xilinx FPGA. The overhead resulting from our reconfiguration scheme are also evaluated and compared to a conventional Booth and array multipliers.

Original languageEnglish
Title of host publicationICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems
Pages975-978
Number of pages4
DOIs
Publication statusPublished - 2007
Externally publishedYes
Event14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007 - Marrakech, Morocco
Duration: 11 Dec 200714 Dec 2007

Other

Other14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007
CountryMorocco
CityMarrakech
Period11/12/0714/12/07

Fingerprint

Field programmable gate arrays (FPGA)

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Shun, Z., Pfänder, O. A., Pfleiderer, H. J., & Bermak, A. (2007). A VLSI architecture for a run-time multi-precision reconfigurable booth multiplier. In ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems (pp. 975-978). [4511155] https://doi.org/10.1109/ICECS.2007.4511155

A VLSI architecture for a run-time multi-precision reconfigurable booth multiplier. / Shun, Zhou; Pfänder, Oliver A.; Pfleiderer, Hans Jörg; Bermak, Amine.

ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems. 2007. p. 975-978 4511155.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Shun, Z, Pfänder, OA, Pfleiderer, HJ & Bermak, A 2007, A VLSI architecture for a run-time multi-precision reconfigurable booth multiplier. in ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems., 4511155, pp. 975-978, 14th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2007, Marrakech, Morocco, 11/12/07. https://doi.org/10.1109/ICECS.2007.4511155
Shun Z, Pfänder OA, Pfleiderer HJ, Bermak A. A VLSI architecture for a run-time multi-precision reconfigurable booth multiplier. In ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems. 2007. p. 975-978. 4511155 https://doi.org/10.1109/ICECS.2007.4511155
Shun, Zhou ; Pfänder, Oliver A. ; Pfleiderer, Hans Jörg ; Bermak, Amine. / A VLSI architecture for a run-time multi-precision reconfigurable booth multiplier. ICECS 2007 - 14th IEEE International Conference on Electronics, Circuits and Systems. 2007. pp. 975-978
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