A very high density VLSI implementation of threshold network ensembles (TNE)

A. Bermak, D. Martinez

Research output: Contribution to journalConference article


This paper describes a hardware implementation of threshold network ensembles (TNE) for classification applications. We first describe the algorithm and compare its performance with those of individual classifiers such as binary neural network and support vector machine (SVM). The effect of limited precision on the performance of threshold network ensembles is also investigated. The proposed multi-precision architecture is then mapped into a scalable systolic architecture implemented first on a single VLSI chip. The modularity and the easy programability of the basic chip has made possible the extension of the architecture to a low cost multichip solution. We propose a 3D packaged circuit in which 12 basic chips have been integrated into a very compact volume of (2 × 2 × 0.7)cm3. Successful operation of the 3D prototype is demonstrated through experimental test results of the chip.

Original languageEnglish
Pages (from-to)617-620
Number of pages4
JournalICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
Publication statusPublished - 25 Sep 2003
Event2003 IEEE International Conference on Accoustics, Speech, and Signal Processing - Hong Kong, Hong Kong
Duration: 6 Apr 200310 Apr 2003


ASJC Scopus subject areas

  • Software
  • Signal Processing
  • Electrical and Electronic Engineering

Cite this