A single bit memory per pixel time domain DPS using multi-reset integration scheme

Sylvain Léomant, Xiajun Wu, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In this paper, a compact time-domain Digital Pixel Sensor (DPS) is proposed. The Pulse Width Modulation (PWM) based sensor employs a multi-reset integration scheme enabling sequential acquisition of high resolution (8-bit) light intensity while using only a single pixel memory. The proposed multi-reset integration method reduces the memory requirements at the pixel-level, without impacting the pixel encoding resolution, as only one bit memory per pixel is required compared to the eight bits memory in conventional pixel architecture. As a consequence, both the pixel size and the fill factor are significantly improved. A near-optimal timing control unit coupled with a linearization circuit is proposed in order to limit the timing penalty incurred by the proposed integration method enabling to maintain high frame rates. A 64x64 sensor array was fabricated using AMS 0.35μm CMOS technology. A pixel size of 23μm x 21μm with a fill factor of 23% is achieved, resulting in over 75% reduction in terms of pixel size and doubling the pixel fill-factor as compared to a conventional 8-bit DPS. Simulation results demonstrate the feasibility of the proposed scheme while achieving a dynamic range higher than 100 dB as well as good linearity of the Analog to Digital Conversion (ADC) response.

Original languageEnglish
Title of host publicationISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems
Pages353-356
Number of pages4
DOIs
Publication statusPublished - 2010
Externally publishedYes
Event2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010 - Paris, France
Duration: 30 May 20102 Jun 2010

Other

Other2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010
CountryFrance
CityParis
Period30/5/102/6/10

Fingerprint

Pixels
Data storage equipment
Sensors
Analog to digital conversion
Sensor arrays
Linearization
Pulse width modulation
Networks (circuits)

Keywords

  • CMOS
  • DPS
  • Fill factor
  • PWM

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Léomant, S., Wu, X., & Bermak, A. (2010). A single bit memory per pixel time domain DPS using multi-reset integration scheme. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems (pp. 353-356). [5537788] https://doi.org/10.1109/ISCAS.2010.5537788

A single bit memory per pixel time domain DPS using multi-reset integration scheme. / Léomant, Sylvain; Wu, Xiajun; Bermak, Amine.

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 353-356 5537788.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Léomant, S, Wu, X & Bermak, A 2010, A single bit memory per pixel time domain DPS using multi-reset integration scheme. in ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems., 5537788, pp. 353-356, 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems, ISCAS 2010, Paris, France, 30/5/10. https://doi.org/10.1109/ISCAS.2010.5537788
Léomant S, Wu X, Bermak A. A single bit memory per pixel time domain DPS using multi-reset integration scheme. In ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. p. 353-356. 5537788 https://doi.org/10.1109/ISCAS.2010.5537788
Léomant, Sylvain ; Wu, Xiajun ; Bermak, Amine. / A single bit memory per pixel time domain DPS using multi-reset integration scheme. ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems. 2010. pp. 353-356
@inproceedings{8c31b422d44c46589abad5971a0de7a1,
title = "A single bit memory per pixel time domain DPS using multi-reset integration scheme",
abstract = "In this paper, a compact time-domain Digital Pixel Sensor (DPS) is proposed. The Pulse Width Modulation (PWM) based sensor employs a multi-reset integration scheme enabling sequential acquisition of high resolution (8-bit) light intensity while using only a single pixel memory. The proposed multi-reset integration method reduces the memory requirements at the pixel-level, without impacting the pixel encoding resolution, as only one bit memory per pixel is required compared to the eight bits memory in conventional pixel architecture. As a consequence, both the pixel size and the fill factor are significantly improved. A near-optimal timing control unit coupled with a linearization circuit is proposed in order to limit the timing penalty incurred by the proposed integration method enabling to maintain high frame rates. A 64x64 sensor array was fabricated using AMS 0.35μm CMOS technology. A pixel size of 23μm x 21μm with a fill factor of 23{\%} is achieved, resulting in over 75{\%} reduction in terms of pixel size and doubling the pixel fill-factor as compared to a conventional 8-bit DPS. Simulation results demonstrate the feasibility of the proposed scheme while achieving a dynamic range higher than 100 dB as well as good linearity of the Analog to Digital Conversion (ADC) response.",
keywords = "CMOS, DPS, Fill factor, PWM",
author = "Sylvain L{\'e}omant and Xiajun Wu and Amine Bermak",
year = "2010",
doi = "10.1109/ISCAS.2010.5537788",
language = "English",
isbn = "9781424453085",
pages = "353--356",
booktitle = "ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems",

}

TY - GEN

T1 - A single bit memory per pixel time domain DPS using multi-reset integration scheme

AU - Léomant, Sylvain

AU - Wu, Xiajun

AU - Bermak, Amine

PY - 2010

Y1 - 2010

N2 - In this paper, a compact time-domain Digital Pixel Sensor (DPS) is proposed. The Pulse Width Modulation (PWM) based sensor employs a multi-reset integration scheme enabling sequential acquisition of high resolution (8-bit) light intensity while using only a single pixel memory. The proposed multi-reset integration method reduces the memory requirements at the pixel-level, without impacting the pixel encoding resolution, as only one bit memory per pixel is required compared to the eight bits memory in conventional pixel architecture. As a consequence, both the pixel size and the fill factor are significantly improved. A near-optimal timing control unit coupled with a linearization circuit is proposed in order to limit the timing penalty incurred by the proposed integration method enabling to maintain high frame rates. A 64x64 sensor array was fabricated using AMS 0.35μm CMOS technology. A pixel size of 23μm x 21μm with a fill factor of 23% is achieved, resulting in over 75% reduction in terms of pixel size and doubling the pixel fill-factor as compared to a conventional 8-bit DPS. Simulation results demonstrate the feasibility of the proposed scheme while achieving a dynamic range higher than 100 dB as well as good linearity of the Analog to Digital Conversion (ADC) response.

AB - In this paper, a compact time-domain Digital Pixel Sensor (DPS) is proposed. The Pulse Width Modulation (PWM) based sensor employs a multi-reset integration scheme enabling sequential acquisition of high resolution (8-bit) light intensity while using only a single pixel memory. The proposed multi-reset integration method reduces the memory requirements at the pixel-level, without impacting the pixel encoding resolution, as only one bit memory per pixel is required compared to the eight bits memory in conventional pixel architecture. As a consequence, both the pixel size and the fill factor are significantly improved. A near-optimal timing control unit coupled with a linearization circuit is proposed in order to limit the timing penalty incurred by the proposed integration method enabling to maintain high frame rates. A 64x64 sensor array was fabricated using AMS 0.35μm CMOS technology. A pixel size of 23μm x 21μm with a fill factor of 23% is achieved, resulting in over 75% reduction in terms of pixel size and doubling the pixel fill-factor as compared to a conventional 8-bit DPS. Simulation results demonstrate the feasibility of the proposed scheme while achieving a dynamic range higher than 100 dB as well as good linearity of the Analog to Digital Conversion (ADC) response.

KW - CMOS

KW - DPS

KW - Fill factor

KW - PWM

UR - http://www.scopus.com/inward/record.url?scp=77955997035&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77955997035&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2010.5537788

DO - 10.1109/ISCAS.2010.5537788

M3 - Conference contribution

SN - 9781424453085

SP - 353

EP - 356

BT - ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

ER -