A simple double mapping based SVPWM method for balancing dc-link capacitor voltages of five-level diode-clamped converters

Aparna Saha, Ali Elrayyah, Yilmaz Sozer

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

DC capacitor voltage imbalances are one of the major technical concerns for higher level diode-clamped converters (DCC). In this paper, a simple double mapping based space vector pulse width modulation (SVPWM) algorithm is proposed for balancing dc-link capacitor voltages of five-level DCC utilizing the switching redundancies. By choosing the appropriate switching pattern and its duration simultaneously, the voltage across each capacitor can be controlled adaptively. The developed mapping approach considers minimum loss SVPWM to address capacitor voltage equalization at high modulation indices. After having all the obtainable switching combinations, the five-level DCC can be mapped into any lower level DCC structure depending on capacitor voltages to increase available switching redundancy. The duty cycles are calculated by taking into account only two-level SVPWM and can be updated for any higher level converter structure by adding required level number. In the proposed scheme dc-capacitor voltage balancing is attained with minimal switching operation, without any requirement of additional auxiliary power circuits. The simulation results validate the capability of mapping based SVPWM strategy to regulate the dc-link capacitor voltages for five-level DCC at different operating conditions.

Original languageEnglish
Title of host publication2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2806-2812
Number of pages7
Volume2016-May
ISBN (Electronic)9781467383936
DOIs
Publication statusPublished - 10 May 2016
Event31st Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2016 - Long Beach, United States
Duration: 20 Mar 201624 Mar 2016

Other

Other31st Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2016
CountryUnited States
CityLong Beach
Period20/3/1624/3/16

Fingerprint

Vector spaces
Pulse width modulation
Diodes
Capacitors
Electric potential
Redundancy
Modulation
Networks (circuits)

Keywords

  • diode-clamped converters(DCC)
  • Five-level (5-level)
  • space vector pulse width modulation (SVPWM)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Saha, A., Elrayyah, A., & Sozer, Y. (2016). A simple double mapping based SVPWM method for balancing dc-link capacitor voltages of five-level diode-clamped converters. In 2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016 (Vol. 2016-May, pp. 2806-2812). [7468262] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APEC.2016.7468262

A simple double mapping based SVPWM method for balancing dc-link capacitor voltages of five-level diode-clamped converters. / Saha, Aparna; Elrayyah, Ali; Sozer, Yilmaz.

2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016. Vol. 2016-May Institute of Electrical and Electronics Engineers Inc., 2016. p. 2806-2812 7468262.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Saha, A, Elrayyah, A & Sozer, Y 2016, A simple double mapping based SVPWM method for balancing dc-link capacitor voltages of five-level diode-clamped converters. in 2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016. vol. 2016-May, 7468262, Institute of Electrical and Electronics Engineers Inc., pp. 2806-2812, 31st Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2016, Long Beach, United States, 20/3/16. https://doi.org/10.1109/APEC.2016.7468262
Saha A, Elrayyah A, Sozer Y. A simple double mapping based SVPWM method for balancing dc-link capacitor voltages of five-level diode-clamped converters. In 2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016. Vol. 2016-May. Institute of Electrical and Electronics Engineers Inc. 2016. p. 2806-2812. 7468262 https://doi.org/10.1109/APEC.2016.7468262
Saha, Aparna ; Elrayyah, Ali ; Sozer, Yilmaz. / A simple double mapping based SVPWM method for balancing dc-link capacitor voltages of five-level diode-clamped converters. 2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016. Vol. 2016-May Institute of Electrical and Electronics Engineers Inc., 2016. pp. 2806-2812
@inproceedings{a28eaef03895424daa398ce813210054,
title = "A simple double mapping based SVPWM method for balancing dc-link capacitor voltages of five-level diode-clamped converters",
abstract = "DC capacitor voltage imbalances are one of the major technical concerns for higher level diode-clamped converters (DCC). In this paper, a simple double mapping based space vector pulse width modulation (SVPWM) algorithm is proposed for balancing dc-link capacitor voltages of five-level DCC utilizing the switching redundancies. By choosing the appropriate switching pattern and its duration simultaneously, the voltage across each capacitor can be controlled adaptively. The developed mapping approach considers minimum loss SVPWM to address capacitor voltage equalization at high modulation indices. After having all the obtainable switching combinations, the five-level DCC can be mapped into any lower level DCC structure depending on capacitor voltages to increase available switching redundancy. The duty cycles are calculated by taking into account only two-level SVPWM and can be updated for any higher level converter structure by adding required level number. In the proposed scheme dc-capacitor voltage balancing is attained with minimal switching operation, without any requirement of additional auxiliary power circuits. The simulation results validate the capability of mapping based SVPWM strategy to regulate the dc-link capacitor voltages for five-level DCC at different operating conditions.",
keywords = "diode-clamped converters(DCC), Five-level (5-level), space vector pulse width modulation (SVPWM)",
author = "Aparna Saha and Ali Elrayyah and Yilmaz Sozer",
year = "2016",
month = "5",
day = "10",
doi = "10.1109/APEC.2016.7468262",
language = "English",
volume = "2016-May",
pages = "2806--2812",
booktitle = "2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - A simple double mapping based SVPWM method for balancing dc-link capacitor voltages of five-level diode-clamped converters

AU - Saha, Aparna

AU - Elrayyah, Ali

AU - Sozer, Yilmaz

PY - 2016/5/10

Y1 - 2016/5/10

N2 - DC capacitor voltage imbalances are one of the major technical concerns for higher level diode-clamped converters (DCC). In this paper, a simple double mapping based space vector pulse width modulation (SVPWM) algorithm is proposed for balancing dc-link capacitor voltages of five-level DCC utilizing the switching redundancies. By choosing the appropriate switching pattern and its duration simultaneously, the voltage across each capacitor can be controlled adaptively. The developed mapping approach considers minimum loss SVPWM to address capacitor voltage equalization at high modulation indices. After having all the obtainable switching combinations, the five-level DCC can be mapped into any lower level DCC structure depending on capacitor voltages to increase available switching redundancy. The duty cycles are calculated by taking into account only two-level SVPWM and can be updated for any higher level converter structure by adding required level number. In the proposed scheme dc-capacitor voltage balancing is attained with minimal switching operation, without any requirement of additional auxiliary power circuits. The simulation results validate the capability of mapping based SVPWM strategy to regulate the dc-link capacitor voltages for five-level DCC at different operating conditions.

AB - DC capacitor voltage imbalances are one of the major technical concerns for higher level diode-clamped converters (DCC). In this paper, a simple double mapping based space vector pulse width modulation (SVPWM) algorithm is proposed for balancing dc-link capacitor voltages of five-level DCC utilizing the switching redundancies. By choosing the appropriate switching pattern and its duration simultaneously, the voltage across each capacitor can be controlled adaptively. The developed mapping approach considers minimum loss SVPWM to address capacitor voltage equalization at high modulation indices. After having all the obtainable switching combinations, the five-level DCC can be mapped into any lower level DCC structure depending on capacitor voltages to increase available switching redundancy. The duty cycles are calculated by taking into account only two-level SVPWM and can be updated for any higher level converter structure by adding required level number. In the proposed scheme dc-capacitor voltage balancing is attained with minimal switching operation, without any requirement of additional auxiliary power circuits. The simulation results validate the capability of mapping based SVPWM strategy to regulate the dc-link capacitor voltages for five-level DCC at different operating conditions.

KW - diode-clamped converters(DCC)

KW - Five-level (5-level)

KW - space vector pulse width modulation (SVPWM)

UR - http://www.scopus.com/inward/record.url?scp=84973643443&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84973643443&partnerID=8YFLogxK

U2 - 10.1109/APEC.2016.7468262

DO - 10.1109/APEC.2016.7468262

M3 - Conference contribution

VL - 2016-May

SP - 2806

EP - 2812

BT - 2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

ER -