A power minimized 74 fJ/conversion-step 88.6 dB SNR incremental ΣΔ ADC with an asynchronous SAR quantizer

Saqib Mohamad, Wu Chao, Jie Yuan, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

Incremental analog to digital converters (lADCs) are aimed at converting low frequency signals with high accuracy. However the use of high oversampling ratios (OSR) usually decreases the conversion speed making them energy inefficient. The first integrator also consumes a lot of power due to high settling requirements, if a single bit quantizer is used. This paper introduces a two step feedforward IADC using an asynchronous Successive Approximation Register (SAR) ADC as a multi-bit quantizer. The same SAR ADC is then used to convert the residue of the incremental conversion. The extended counting enables high conversion speed and the use of a multibit quantizer reduces settling requirements for the first integrator. As a result, high power efficiency is achieved. The ADC achieves a peak SNR of 88.6 dB within a Nyquist bandwidth of 2.5 kHz, with a power consumption of only 8.44 μW. The measured Waiden and Schreier FoMs are 74 fj/conv.-step and 173.3 dB, respectively.

Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and Systems
Subtitle of host publicationFrom Dreams to Innovation, ISCAS 2017 - Conference Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467368520
DOIs
Publication statusPublished - 25 Sep 2017
Event50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 - Baltimore, United States
Duration: 28 May 201731 May 2017

Other

Other50th IEEE International Symposium on Circuits and Systems, ISCAS 2017
CountryUnited States
CityBaltimore
Period28/5/1731/5/17

Fingerprint

Digital to analog conversion
Electric power utilization
Bandwidth

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Mohamad, S., Chao, W., Yuan, J., & Bermak, A. (2017). A power minimized 74 fJ/conversion-step 88.6 dB SNR incremental ΣΔ ADC with an asynchronous SAR quantizer. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings [8050248] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS.2017.8050248

A power minimized 74 fJ/conversion-step 88.6 dB SNR incremental ΣΔ ADC with an asynchronous SAR quantizer. / Mohamad, Saqib; Chao, Wu; Yuan, Jie; Bermak, Amine.

IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017. 8050248.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mohamad, S, Chao, W, Yuan, J & Bermak, A 2017, A power minimized 74 fJ/conversion-step 88.6 dB SNR incremental ΣΔ ADC with an asynchronous SAR quantizer. in IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings., 8050248, Institute of Electrical and Electronics Engineers Inc., 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, United States, 28/5/17. https://doi.org/10.1109/ISCAS.2017.8050248
Mohamad S, Chao W, Yuan J, Bermak A. A power minimized 74 fJ/conversion-step 88.6 dB SNR incremental ΣΔ ADC with an asynchronous SAR quantizer. In IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc. 2017. 8050248 https://doi.org/10.1109/ISCAS.2017.8050248
Mohamad, Saqib ; Chao, Wu ; Yuan, Jie ; Bermak, Amine. / A power minimized 74 fJ/conversion-step 88.6 dB SNR incremental ΣΔ ADC with an asynchronous SAR quantizer. IEEE International Symposium on Circuits and Systems: From Dreams to Innovation, ISCAS 2017 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2017.
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