A novel scalable spiking pixel architecture for deep submicron CMOS technologies

Farid Boussaid, Chen Shoushun, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, we propose a scalable spiking pixel architecture for deep submicron CMOS technologies. The proposed pixel architecture uniquely combines counting and memory functions into a single compact circuit, providing for in-pixel storage capability, in-pixel analog-to-digital conversion and random read-out of digital pixel values. Pixel fill-factor is better than 15% for a 50×50μm pixel fabricated using AMI 0.35μm CMOS technology. Reported experimental results validate the proposed spiking pixel architecture for the next generation of deep submicron silicon processes.

Original languageEnglish
Title of host publicationProceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006
Pages131-135
Number of pages5
Publication statusPublished - 1 Dec 2006
Event2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006 - Tunis, Tunisia
Duration: 5 Sep 20067 Sep 2006

Publication series

NameProceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006

Other

Other2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006
CountryTunisia
CityTunis
Period5/9/067/9/06

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ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

Cite this

Boussaid, F., Shoushun, C., & Bermak, A. (2006). A novel scalable spiking pixel architecture for deep submicron CMOS technologies. In Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006 (pp. 131-135). [1708718] (Proceedings - 2006 International Conference on Design and Test of Integrated Systems in Nanoscale Technology, IEEE DTIS 2006).