A novel memory subsystem evaluation framework for chip multiprocessors

Fucen Zeng, Lin Qiao, Mingliang Liu, Zhizhong Tang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents a fast and cycle-accurate memory subsystem modeling and evaluating framework for Chip Multiprocessors (CMPs), called TSIM (Tsinghua SIMulator), which gives a flexible and extensible approach to evaluating architecture designs, models or algorithms, including the network-on-chip interconnection, cache hardware prefetcher, memory system protocol, replacement policy, etc. TSIM is trace-driven, adopting a dynamic binary instrumentation technique to generate the running trace information of applications on-the-fly. After receiving the trace information, TSIM will reappear the on-chip memory behaviors of applications. By introducing the concept of statistical meta metrics, TSIM separates the analysis stage from the simulation process per se, and this provides a great facilitation for a user to count and sample the performance metrics. Compared to the real cache system, TSIM achieves an accuracy of 90.66% at the average speed of 327 KIPS. Meanwhile, TSIM accelerates the simulating speed by almost 10 times, compared to the traditional cycle-accurate cache simulators. On the other hand, when TSIM is used to characterize the onchip memory system behaviors of SPEC CPU 2000 benchmarks, experimental results about the on-chip memory behaviors are the same as others.

Original languageEnglish
Title of host publicationProceedings - 2010 12th IEEE International Conference on High Performance Computing and Communications, HPCC 2010
Pages231-238
Number of pages8
DOIs
Publication statusPublished - 15 Nov 2010
Event2010 12th IEEE International Conference on High Performance Computing and Communications, HPCC 2010 - Melbourne, VIC
Duration: 1 Sep 20103 Sep 2010

Other

Other2010 12th IEEE International Conference on High Performance Computing and Communications, HPCC 2010
CityMelbourne, VIC
Period1/9/103/9/10

Fingerprint

Chip multiprocessors
Subsystem
Simulator
Simulators
Data storage equipment
Evaluation
Cache
Trace
Computer systems
Chip
Cycle
Replacement Policy
Framework
Process Simulation
Performance Metrics
Instrumentation
Interconnection
Computer hardware
Accelerate
Program processors

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Theoretical Computer Science

Cite this

Zeng, F., Qiao, L., Liu, M., & Tang, Z. (2010). A novel memory subsystem evaluation framework for chip multiprocessors. In Proceedings - 2010 12th IEEE International Conference on High Performance Computing and Communications, HPCC 2010 (pp. 231-238). [5581346] https://doi.org/10.1109/HPCC.2010.15

A novel memory subsystem evaluation framework for chip multiprocessors. / Zeng, Fucen; Qiao, Lin; Liu, Mingliang; Tang, Zhizhong.

Proceedings - 2010 12th IEEE International Conference on High Performance Computing and Communications, HPCC 2010. 2010. p. 231-238 5581346.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zeng, F, Qiao, L, Liu, M & Tang, Z 2010, A novel memory subsystem evaluation framework for chip multiprocessors. in Proceedings - 2010 12th IEEE International Conference on High Performance Computing and Communications, HPCC 2010., 5581346, pp. 231-238, 2010 12th IEEE International Conference on High Performance Computing and Communications, HPCC 2010, Melbourne, VIC, 1/9/10. https://doi.org/10.1109/HPCC.2010.15
Zeng F, Qiao L, Liu M, Tang Z. A novel memory subsystem evaluation framework for chip multiprocessors. In Proceedings - 2010 12th IEEE International Conference on High Performance Computing and Communications, HPCC 2010. 2010. p. 231-238. 5581346 https://doi.org/10.1109/HPCC.2010.15
Zeng, Fucen ; Qiao, Lin ; Liu, Mingliang ; Tang, Zhizhong. / A novel memory subsystem evaluation framework for chip multiprocessors. Proceedings - 2010 12th IEEE International Conference on High Performance Computing and Communications, HPCC 2010. 2010. pp. 231-238
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