A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18 μm CMOS technology

Chen Xu, Chao Shen, Amine Bermak, Mansun Chan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

11 Citations (Scopus)

Abstract

In this paper, a digital pixel architecture with pixel-level ADC based on Pulse Width Modulation (PWM) scheme and an 8-bit DRAM is proposed to operate at an extremely low voltage environment, i.e., 1.2V. This digital pixel architecture is designed to eliminate the restriction of low supply voltage imposed by device scaling trend. The pixel is implemented in a commercially available 0.18μm, single poly and 6 metal CMOS process. Simulation results show that the circuit is functional at a VDD of 1.2V with a higher dynamic range and lower power consumption as compared to conventional CMOS APS architecture.

Original languageEnglish
Title of host publication2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages265-268
Number of pages4
ISBN (Electronic)0780377494, 9780780377493
DOIs
Publication statusPublished - 2003
Externally publishedYes
EventIEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 - Tsimshatsui, Kowloon, Hong Kong
Duration: 16 Dec 200318 Dec 2003

Other

OtherIEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003
CountryHong Kong
CityTsimshatsui, Kowloon
Period16/12/0318/12/03

Fingerprint

Image sensors
Pulse width modulation
Pixels
Dynamic random access storage
Electric potential
Electric power utilization
Networks (circuits)
Metals

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Xu, C., Shen, C., Bermak, A., & Chan, M. (2003). A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18 μm CMOS technology. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003 (pp. 265-268). [1283528] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2003.1283528

A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18 μm CMOS technology. / Xu, Chen; Shen, Chao; Bermak, Amine; Chan, Mansun.

2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 265-268 1283528.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Xu, C, Shen, C, Bermak, A & Chan, M 2003, A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18 μm CMOS technology. in 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003., 1283528, Institute of Electrical and Electronics Engineers Inc., pp. 265-268, IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003, Tsimshatsui, Kowloon, Hong Kong, 16/12/03. https://doi.org/10.1109/EDSSC.2003.1283528
Xu C, Shen C, Bermak A, Chan M. A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18 μm CMOS technology. In 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 265-268. 1283528 https://doi.org/10.1109/EDSSC.2003.1283528
Xu, Chen ; Shen, Chao ; Bermak, Amine ; Chan, Mansun. / A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18 μm CMOS technology. 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 265-268
@inproceedings{5734066d502444e08ec7101749c7c8f3,
title = "A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18 μm CMOS technology",
abstract = "In this paper, a digital pixel architecture with pixel-level ADC based on Pulse Width Modulation (PWM) scheme and an 8-bit DRAM is proposed to operate at an extremely low voltage environment, i.e., 1.2V. This digital pixel architecture is designed to eliminate the restriction of low supply voltage imposed by device scaling trend. The pixel is implemented in a commercially available 0.18μm, single poly and 6 metal CMOS process. Simulation results show that the circuit is functional at a VDD of 1.2V with a higher dynamic range and lower power consumption as compared to conventional CMOS APS architecture.",
author = "Chen Xu and Chao Shen and Amine Bermak and Mansun Chan",
year = "2003",
doi = "10.1109/EDSSC.2003.1283528",
language = "English",
pages = "265--268",
booktitle = "2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

TY - GEN

T1 - A new digital-pixel architecture for CMOS image sensor with pixel-level ADC and pulse width modulation using a 0.18 μm CMOS technology

AU - Xu, Chen

AU - Shen, Chao

AU - Bermak, Amine

AU - Chan, Mansun

PY - 2003

Y1 - 2003

N2 - In this paper, a digital pixel architecture with pixel-level ADC based on Pulse Width Modulation (PWM) scheme and an 8-bit DRAM is proposed to operate at an extremely low voltage environment, i.e., 1.2V. This digital pixel architecture is designed to eliminate the restriction of low supply voltage imposed by device scaling trend. The pixel is implemented in a commercially available 0.18μm, single poly and 6 metal CMOS process. Simulation results show that the circuit is functional at a VDD of 1.2V with a higher dynamic range and lower power consumption as compared to conventional CMOS APS architecture.

AB - In this paper, a digital pixel architecture with pixel-level ADC based on Pulse Width Modulation (PWM) scheme and an 8-bit DRAM is proposed to operate at an extremely low voltage environment, i.e., 1.2V. This digital pixel architecture is designed to eliminate the restriction of low supply voltage imposed by device scaling trend. The pixel is implemented in a commercially available 0.18μm, single poly and 6 metal CMOS process. Simulation results show that the circuit is functional at a VDD of 1.2V with a higher dynamic range and lower power consumption as compared to conventional CMOS APS architecture.

UR - http://www.scopus.com/inward/record.url?scp=35648967588&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=35648967588&partnerID=8YFLogxK

U2 - 10.1109/EDSSC.2003.1283528

DO - 10.1109/EDSSC.2003.1283528

M3 - Conference contribution

SP - 265

EP - 268

BT - 2003 IEEE Conference on Electron Devices and Solid-State Circuits, EDSSC 2003

PB - Institute of Electrical and Electronics Engineers Inc.

ER -