Minimum-area very large scale integration (VLSI) networks have been proposed for sorting N elements in O(log N) time. However, most such networks proposed have complex structure, and no explicit network construction was given in others. This paper presents new designs of optimal VLSI sorters, which combine rotate-sort with enumeration-sort to sort N numbers, each of length w = (1 + є) log N bits (for any constant є < 0), in time T є[Ω(log N),. The main attributes of the proposed sorters are a significantly smaller number of sorting nodes than in previous designs and smaller constant factors in their time complexity. The proposed sorters use a new class of reduced-area K-shuffle layouts to route data between sorting stages. These layouts can be also used to provide explicit designs for Leighton’s column-sort technique.
ASJC Scopus subject areas
- Theoretical Computer Science
- Hardware and Architecture
- Computational Theory and Mathematics