A low-power dynamic comparator with digital calibration for reduced offset mismatch

Denis Guangyin Chen, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

This paper describes a fully dynamic analog comparator with digital calibration for very low offset error. In this work, we propose an off-line calibration scheme where the offset error is quantized by successive approximation. During run-time, the offset is cancelled by a digital-to-analog converter (DAC). We further improve the robustness of this cancellation by using a redundant cell to compensate for any internal mismatch within the DAC. Simulation in 0.18 um CMOS technology shows that our scheme can reduce the offset error to less than 0.86 mV rms under 1.8 V supply. The comparator consumes 1.4 pJ, and the clock to data delay is 3.5 ns.

Original languageEnglish
Title of host publicationISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems
Pages1283-1286
Number of pages4
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012

Other

Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period20/5/1223/5/12

Fingerprint

Calibration
Digital to analog conversion
Clocks

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chen, D. G., & Bermak, A. (2012). A low-power dynamic comparator with digital calibration for reduced offset mismatch. In ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems (pp. 1283-1286). [6271472] https://doi.org/10.1109/ISCAS.2012.6271472

A low-power dynamic comparator with digital calibration for reduced offset mismatch. / Chen, Denis Guangyin; Bermak, Amine.

ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems. 2012. p. 1283-1286 6271472.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Chen, DG & Bermak, A 2012, A low-power dynamic comparator with digital calibration for reduced offset mismatch. in ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems., 6271472, pp. 1283-1286, 2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012, Seoul, Korea, Republic of, 20/5/12. https://doi.org/10.1109/ISCAS.2012.6271472
Chen DG, Bermak A. A low-power dynamic comparator with digital calibration for reduced offset mismatch. In ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems. 2012. p. 1283-1286. 6271472 https://doi.org/10.1109/ISCAS.2012.6271472
Chen, Denis Guangyin ; Bermak, Amine. / A low-power dynamic comparator with digital calibration for reduced offset mismatch. ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems. 2012. pp. 1283-1286
@inproceedings{457ec46171e243ada655312357e114e8,
title = "A low-power dynamic comparator with digital calibration for reduced offset mismatch",
abstract = "This paper describes a fully dynamic analog comparator with digital calibration for very low offset error. In this work, we propose an off-line calibration scheme where the offset error is quantized by successive approximation. During run-time, the offset is cancelled by a digital-to-analog converter (DAC). We further improve the robustness of this cancellation by using a redundant cell to compensate for any internal mismatch within the DAC. Simulation in 0.18 um CMOS technology shows that our scheme can reduce the offset error to less than 0.86 mV rms under 1.8 V supply. The comparator consumes 1.4 pJ, and the clock to data delay is 3.5 ns.",
author = "Chen, {Denis Guangyin} and Amine Bermak",
year = "2012",
doi = "10.1109/ISCAS.2012.6271472",
language = "English",
pages = "1283--1286",
booktitle = "ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems",

}

TY - GEN

T1 - A low-power dynamic comparator with digital calibration for reduced offset mismatch

AU - Chen, Denis Guangyin

AU - Bermak, Amine

PY - 2012

Y1 - 2012

N2 - This paper describes a fully dynamic analog comparator with digital calibration for very low offset error. In this work, we propose an off-line calibration scheme where the offset error is quantized by successive approximation. During run-time, the offset is cancelled by a digital-to-analog converter (DAC). We further improve the robustness of this cancellation by using a redundant cell to compensate for any internal mismatch within the DAC. Simulation in 0.18 um CMOS technology shows that our scheme can reduce the offset error to less than 0.86 mV rms under 1.8 V supply. The comparator consumes 1.4 pJ, and the clock to data delay is 3.5 ns.

AB - This paper describes a fully dynamic analog comparator with digital calibration for very low offset error. In this work, we propose an off-line calibration scheme where the offset error is quantized by successive approximation. During run-time, the offset is cancelled by a digital-to-analog converter (DAC). We further improve the robustness of this cancellation by using a redundant cell to compensate for any internal mismatch within the DAC. Simulation in 0.18 um CMOS technology shows that our scheme can reduce the offset error to less than 0.86 mV rms under 1.8 V supply. The comparator consumes 1.4 pJ, and the clock to data delay is 3.5 ns.

UR - http://www.scopus.com/inward/record.url?scp=84866613069&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84866613069&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2012.6271472

DO - 10.1109/ISCAS.2012.6271472

M3 - Conference contribution

SP - 1283

EP - 1286

BT - ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems

ER -