A low-power dynamic comparator with digital calibration for reduced offset mismatch

Denis Guangyin Chen, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

This paper describes a fully dynamic analog comparator with digital calibration for very low offset error. In this work, we propose an off-line calibration scheme where the offset error is quantized by successive approximation. During run-time, the offset is cancelled by a digital-to-analog converter (DAC). We further improve the robustness of this cancellation by using a redundant cell to compensate for any internal mismatch within the DAC. Simulation in 0.18 um CMOS technology shows that our scheme can reduce the offset error to less than 0.86 mV rms under 1.8 V supply. The comparator consumes 1.4 pJ, and the clock to data delay is 3.5 ns.

Original languageEnglish
Title of host publicationISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems
Pages1283-1286
Number of pages4
DOIs
Publication statusPublished - 2012
Externally publishedYes
Event2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, Korea, Republic of
Duration: 20 May 201223 May 2012

Other

Other2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
CountryKorea, Republic of
CitySeoul
Period20/5/1223/5/12

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Chen, D. G., & Bermak, A. (2012). A low-power dynamic comparator with digital calibration for reduced offset mismatch. In ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems (pp. 1283-1286). [6271472] https://doi.org/10.1109/ISCAS.2012.6271472