A low power digital pixel sensor with a dynamically biased ADC

Xiajun Wu, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

In this paper,a low power CMOS image sensor using DPS scheme is proposed. A sub-threshold control unit is used in order to enable or disable the pixel level ADC depending on the photodiode sensing voltage, hence enabling to save the static power needed to operate the pixel level ADC.Results show that up to 90% power saving is achieved when compared with the conventional Digital Pixel Sensor. To compensate for the nonlinearity of the proposed time-domain ADC a clock modulation compensation scheme is proposed which can be fully implemented in digital. The sensor was implemented in 0.35um CMOS process and the sensor operation is successfully tested.

Original languageEnglish
Title of host publication2008 International SoC Design Conference, ISOCC 2008
Volume1
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 International SoC Design Conference, ISOCC 2008 - Busan, Korea, Republic of
Duration: 24 Nov 200825 Nov 2008

Other

Other2008 International SoC Design Conference, ISOCC 2008
CountryKorea, Republic of
CityBusan
Period24/11/0825/11/08

Fingerprint

Pixels
Sensors
Photodiodes
Image sensors
Clocks
Modulation
Electric potential
Compensation and Redress

ASJC Scopus subject areas

  • Hardware and Architecture
  • Software

Cite this

Wu, X., & Bermak, A. (2008). A low power digital pixel sensor with a dynamically biased ADC. In 2008 International SoC Design Conference, ISOCC 2008 (Vol. 1). [4815584] https://doi.org/10.1109/SOCDC.2008.4815584

A low power digital pixel sensor with a dynamically biased ADC. / Wu, Xiajun; Bermak, Amine.

2008 International SoC Design Conference, ISOCC 2008. Vol. 1 2008. 4815584.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wu, X & Bermak, A 2008, A low power digital pixel sensor with a dynamically biased ADC. in 2008 International SoC Design Conference, ISOCC 2008. vol. 1, 4815584, 2008 International SoC Design Conference, ISOCC 2008, Busan, Korea, Republic of, 24/11/08. https://doi.org/10.1109/SOCDC.2008.4815584
Wu X, Bermak A. A low power digital pixel sensor with a dynamically biased ADC. In 2008 International SoC Design Conference, ISOCC 2008. Vol. 1. 2008. 4815584 https://doi.org/10.1109/SOCDC.2008.4815584
Wu, Xiajun ; Bermak, Amine. / A low power digital pixel sensor with a dynamically biased ADC. 2008 International SoC Design Conference, ISOCC 2008. Vol. 1 2008.
@inproceedings{fb79de9011e24ff48859c5be012a8123,
title = "A low power digital pixel sensor with a dynamically biased ADC",
abstract = "In this paper,a low power CMOS image sensor using DPS scheme is proposed. A sub-threshold control unit is used in order to enable or disable the pixel level ADC depending on the photodiode sensing voltage, hence enabling to save the static power needed to operate the pixel level ADC.Results show that up to 90{\%} power saving is achieved when compared with the conventional Digital Pixel Sensor. To compensate for the nonlinearity of the proposed time-domain ADC a clock modulation compensation scheme is proposed which can be fully implemented in digital. The sensor was implemented in 0.35um CMOS process and the sensor operation is successfully tested.",
author = "Xiajun Wu and Amine Bermak",
year = "2008",
doi = "10.1109/SOCDC.2008.4815584",
language = "English",
isbn = "9781424425990",
volume = "1",
booktitle = "2008 International SoC Design Conference, ISOCC 2008",

}

TY - GEN

T1 - A low power digital pixel sensor with a dynamically biased ADC

AU - Wu, Xiajun

AU - Bermak, Amine

PY - 2008

Y1 - 2008

N2 - In this paper,a low power CMOS image sensor using DPS scheme is proposed. A sub-threshold control unit is used in order to enable or disable the pixel level ADC depending on the photodiode sensing voltage, hence enabling to save the static power needed to operate the pixel level ADC.Results show that up to 90% power saving is achieved when compared with the conventional Digital Pixel Sensor. To compensate for the nonlinearity of the proposed time-domain ADC a clock modulation compensation scheme is proposed which can be fully implemented in digital. The sensor was implemented in 0.35um CMOS process and the sensor operation is successfully tested.

AB - In this paper,a low power CMOS image sensor using DPS scheme is proposed. A sub-threshold control unit is used in order to enable or disable the pixel level ADC depending on the photodiode sensing voltage, hence enabling to save the static power needed to operate the pixel level ADC.Results show that up to 90% power saving is achieved when compared with the conventional Digital Pixel Sensor. To compensate for the nonlinearity of the proposed time-domain ADC a clock modulation compensation scheme is proposed which can be fully implemented in digital. The sensor was implemented in 0.35um CMOS process and the sensor operation is successfully tested.

UR - http://www.scopus.com/inward/record.url?scp=69949085066&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=69949085066&partnerID=8YFLogxK

U2 - 10.1109/SOCDC.2008.4815584

DO - 10.1109/SOCDC.2008.4815584

M3 - Conference contribution

SN - 9781424425990

VL - 1

BT - 2008 International SoC Design Conference, ISOCC 2008

ER -