Abstract
In this paper, we describe an integrating current-mode CMOS pixel based on a novel reset/read-out strategy. In contrast to the conventional integrating mode pixel, here the reset and read-out phases of the imager are carried out simultaneously. In the new read-out strategy, only two current sources are enabled at any given time, resulting in a power consumption that is independent of both read-out speed and imager array size, while still allowing for on read-out FPN cancellation. The addressing signals of the proposed read-out strategy are generated using conventional counters and an address decoders, which are also used to generate the addressing signals required for an electronic shutter, resulting in significant saving in silicon area. To demonstrate the benefits of the proposed approach and the pixel operation, a 32 × 32 imager has been integrated using AMIS CMOS 0.35μm technology.
| Original language | English |
|---|---|
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 2 |
| Publication status | Published - 2004 |
| Externally published | Yes |
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ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
A low power current-mode pixel with on-chip FPN cancellation and digital shutter. / Bermak, Amine; Boussaïd, Farid; Bouzerdoum, Abdesselam.
In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 2, 2004.Research output: Contribution to journal › Article
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TY - JOUR
T1 - A low power current-mode pixel with on-chip FPN cancellation and digital shutter
AU - Bermak, Amine
AU - Boussaïd, Farid
AU - Bouzerdoum, Abdesselam
PY - 2004
Y1 - 2004
N2 - In this paper, we describe an integrating current-mode CMOS pixel based on a novel reset/read-out strategy. In contrast to the conventional integrating mode pixel, here the reset and read-out phases of the imager are carried out simultaneously. In the new read-out strategy, only two current sources are enabled at any given time, resulting in a power consumption that is independent of both read-out speed and imager array size, while still allowing for on read-out FPN cancellation. The addressing signals of the proposed read-out strategy are generated using conventional counters and an address decoders, which are also used to generate the addressing signals required for an electronic shutter, resulting in significant saving in silicon area. To demonstrate the benefits of the proposed approach and the pixel operation, a 32 × 32 imager has been integrated using AMIS CMOS 0.35μm technology.
AB - In this paper, we describe an integrating current-mode CMOS pixel based on a novel reset/read-out strategy. In contrast to the conventional integrating mode pixel, here the reset and read-out phases of the imager are carried out simultaneously. In the new read-out strategy, only two current sources are enabled at any given time, resulting in a power consumption that is independent of both read-out speed and imager array size, while still allowing for on read-out FPN cancellation. The addressing signals of the proposed read-out strategy are generated using conventional counters and an address decoders, which are also used to generate the addressing signals required for an electronic shutter, resulting in significant saving in silicon area. To demonstrate the benefits of the proposed approach and the pixel operation, a 32 × 32 imager has been integrated using AMIS CMOS 0.35μm technology.
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M3 - Article
AN - SCOPUS:4344704915
VL - 2
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
ER -