A low-offset dynamic comparator with area-efficient and low-power offset cancellation

Xiaopeng Zhong, Amine Bermak, Chi Ying Tsui

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A low-offset two-stage dynamic comparator has been proposed for parallel multi-channel processing. Low offset is achieved from two aspects: 1st-stage offset cancellation and 2nd-stage offset suppression. A fully dynamic offset cancellation scheme based on current auto-zeroing is adopted to effectively cancel out the 1st-stage offset. It features small area overhead and low energy consumption. For the 2nd-stage offset suppression, a high gain is designed for the 1st-stage dynamic amplifier by optimizing the overdrive voltage of input transistors. To maintain low offset performance across a wide range of input commonmode voltages, the overdrive voltage of the input pair is required to stay low. Therefore, a tail current source is employed for the 1st stage to ensure constant common-mode discharging current. As a result, the overdrive voltage can be stably kept low under various operation conditions. The proposed comparator has been designed in a standard CMOS 0.18 μm process. It operates under a supply voltage of 1.2 V at 10 MHz. Simulation results have verified the low-offset property of the comparator. The input-referred offset (1 σ) is reduced from 19.25 mV to 1.296 mV after cancellation and it remains constant with the input commonmode voltage changing from 0 V to 0.8 V. The offset is further reduced to 771 μV when the 2nd-stage input pair are enlarged by 4 times. At the same time, the energy consumption is increased from 147 fJ/Conv to 168 fJ/Conv.

Original languageEnglish
Title of host publication25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings
PublisherIEEE Computer Society
ISBN (Electronic)9781538628805
DOIs
Publication statusPublished - 13 Dec 2017
Event25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Abu Dhabi, United Arab Emirates
Duration: 23 Oct 201725 Oct 2017

Other

Other25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017
CountryUnited Arab Emirates
CityAbu Dhabi
Period23/10/1725/10/17

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ASJC Scopus subject areas

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Zhong, X., Bermak, A., & Tsui, C. Y. (2017). A low-offset dynamic comparator with area-efficient and low-power offset cancellation. In 25th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2017 - Proceedings [8203481] IEEE Computer Society. https://doi.org/10.1109/VLSI-SoC.2017.8203481