A ladder transistor-clamped multilevel inverter with high-voltage variation

Eshet T. Wodajo, Malik Elbuluk, Seungdeog Choi, Haitham Abu-Rub

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, a new ladder transistor clamped multilevel inverter topology is proposed with the aim of reducing the number of transistor, while maintaining the bidirectionalcontrolled current flow capability of the transistor-clamped topologies. The basic structural features of the topology are presented along with their operational purpose. The merits of the new topology with respect to other topologies in the low-voltage and high-voltage operations are discussed. In addition, the semimodular characteristics of the structure are discussed in regard to the scalability of the topology. Finally, the validity of the structure is demonstrated using simulation results for different voltage variations of the topology and a three-phase structure.

Original languageEnglish
Title of host publication2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages5679-5684
Number of pages6
Volume2017-January
ISBN (Electronic)9781509029983
DOIs
Publication statusPublished - 3 Nov 2017
Event9th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2017 - Cincinnati, United States
Duration: 1 Oct 20175 Oct 2017

Other

Other9th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2017
CountryUnited States
CityCincinnati
Period1/10/175/10/17

Fingerprint

Ladders
Inverter
Transistors
Voltage
Topology
Electric potential
Low Voltage
Phase structure
Scalability
Simulation

Keywords

  • High Voltage.
  • Ladder Topology
  • Multilevel Inverter
  • Scalability
  • Transistor-Clamped

ASJC Scopus subject areas

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering
  • Renewable Energy, Sustainability and the Environment
  • Control and Optimization

Cite this

Wodajo, E. T., Elbuluk, M., Choi, S., & Abu-Rub, H. (2017). A ladder transistor-clamped multilevel inverter with high-voltage variation. In 2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017 (Vol. 2017-January, pp. 5679-5684). [8096944] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ECCE.2017.8096944

A ladder transistor-clamped multilevel inverter with high-voltage variation. / Wodajo, Eshet T.; Elbuluk, Malik; Choi, Seungdeog; Abu-Rub, Haitham.

2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017. Vol. 2017-January Institute of Electrical and Electronics Engineers Inc., 2017. p. 5679-5684 8096944.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wodajo, ET, Elbuluk, M, Choi, S & Abu-Rub, H 2017, A ladder transistor-clamped multilevel inverter with high-voltage variation. in 2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017. vol. 2017-January, 8096944, Institute of Electrical and Electronics Engineers Inc., pp. 5679-5684, 9th Annual IEEE Energy Conversion Congress and Exposition, ECCE 2017, Cincinnati, United States, 1/10/17. https://doi.org/10.1109/ECCE.2017.8096944
Wodajo ET, Elbuluk M, Choi S, Abu-Rub H. A ladder transistor-clamped multilevel inverter with high-voltage variation. In 2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017. Vol. 2017-January. Institute of Electrical and Electronics Engineers Inc. 2017. p. 5679-5684. 8096944 https://doi.org/10.1109/ECCE.2017.8096944
Wodajo, Eshet T. ; Elbuluk, Malik ; Choi, Seungdeog ; Abu-Rub, Haitham. / A ladder transistor-clamped multilevel inverter with high-voltage variation. 2017 IEEE Energy Conversion Congress and Exposition, ECCE 2017. Vol. 2017-January Institute of Electrical and Electronics Engineers Inc., 2017. pp. 5679-5684
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