A highly scalable 3D chip for binary neural network classification applications

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4 Citations (Scopus)

Abstract

This paper describes a 3D VLSI Chip for binary neural network classification applications. The 3D circuit includes three layers of MCM integrating 4 chips each making it a total of 12 chips integrated in a volume of (2 × 2 × 0.7)cm3. The architecture is scalable, and real-time binary neural network classifier systems could be built with one, two or all twelve chip solutions. Each basic chip includes an on-chip control unit for programming options of the neural network topology and precision. The system is modular and presents easy expansibility without requiring extra devices. Experimental test results showed that a full recall operation is obtained in less than 1.2μs for any topology with 4-bit or 8-bit precision while it is obtained in less than 2.2μs for any 16-bit precision. As a consequence the 3D chip is a very powerful reconfigurable and a multiprecision neural chip exhibiting a significant speed of 1.25 GCPS.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume5
Publication statusPublished - 2003
Externally publishedYes

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Neural networks
Topology
Multicarrier modulation
Classifiers
Networks (circuits)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

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title = "A highly scalable 3D chip for binary neural network classification applications",
abstract = "This paper describes a 3D VLSI Chip for binary neural network classification applications. The 3D circuit includes three layers of MCM integrating 4 chips each making it a total of 12 chips integrated in a volume of (2 × 2 × 0.7)cm3. The architecture is scalable, and real-time binary neural network classifier systems could be built with one, two or all twelve chip solutions. Each basic chip includes an on-chip control unit for programming options of the neural network topology and precision. The system is modular and presents easy expansibility without requiring extra devices. Experimental test results showed that a full recall operation is obtained in less than 1.2μs for any topology with 4-bit or 8-bit precision while it is obtained in less than 2.2μs for any 16-bit precision. As a consequence the 3D chip is a very powerful reconfigurable and a multiprecision neural chip exhibiting a significant speed of 1.25 GCPS.",
author = "Amine Bermak",
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AB - This paper describes a 3D VLSI Chip for binary neural network classification applications. The 3D circuit includes three layers of MCM integrating 4 chips each making it a total of 12 chips integrated in a volume of (2 × 2 × 0.7)cm3. The architecture is scalable, and real-time binary neural network classifier systems could be built with one, two or all twelve chip solutions. Each basic chip includes an on-chip control unit for programming options of the neural network topology and precision. The system is modular and presents easy expansibility without requiring extra devices. Experimental test results showed that a full recall operation is obtained in less than 1.2μs for any topology with 4-bit or 8-bit precision while it is obtained in less than 2.2μs for any 16-bit precision. As a consequence the 3D chip is a very powerful reconfigurable and a multiprecision neural chip exhibiting a significant speed of 1.25 GCPS.

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