A high-speed 32-bit signed/unsigned pipelined multiplier

Qingzheng Li, Guixuan Liang, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

In this paper, a novel unified implementation of signed/unsigned multiplication is proposed using a simple sign-control unit together with a line of multiplexers. The proposed approach is demonstrated through a 0.18μm CMOS implementation of a 32-bit signed/unsigned multiplier. Reported results show that the proposed unified signed/unsigned implementation is very compact with only 0.45% silicon area overhead. The critical path delay of the proposed multiplier is about 3.13ns.

Original languageEnglish
Title of host publicationProceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010
Pages207-211
Number of pages5
DOIs
Publication statusPublished - 21 May 2010
Event5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010 - Ho Chi Minh City, Viet Nam
Duration: 13 Jan 201015 Jan 2010

Publication series

NameProceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010

Other

Other5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010
CountryViet Nam
CityHo Chi Minh City
Period13/1/1015/1/10

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Keywords

  • Booth encoding
  • Fast adder
  • Signed/unsigned multiplier
  • Wallace tree

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Li, Q., Liang, G., & Bermak, A. (2010). A high-speed 32-bit signed/unsigned pipelined multiplier. In Proceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010 (pp. 207-211). [5438690] (Proceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010). https://doi.org/10.1109/DELTA.2010.10