A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter

Yat Fong Yung, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper a CMOS image sensor with on-pixel analog-to-digital convener based on PWM scheme is proposed. The digital pixel sensor includes a novel digital circuit which allows to configure the internal 8-bit memory as a 4-bit counter/memory, so as to reduce the data bit lines routed to each pixel from 8-bit to 4-bit. Hence the total parasitic capacitance as well as power consumption associated with the switching activities of the global data bus lines are reduced. Besides 8-bit precision, the imager can also be configured to 4-bit precision for low resolution applications, which has the advantage of increasing frame rate and decreasing overall power consumption. A prototype chip was realized in Alcatel 0.35μm CMOS technology. Each pixel occupies an area of 46μm × 48μm with a fill-factor of 14%.

Original languageEnglish
Title of host publicationProceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004
EditorsW. Badawy, Y. Ismail
Pages33-36
Number of pages4
Publication statusPublished - 2004
Externally publishedYes
EventProceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004 - Banff, Alta, Canada
Duration: 19 Jul 200421 Jul 2004

Other

OtherProceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004
CountryCanada
CityBanff, Alta
Period19/7/0421/7/04

Fingerprint

Static random access storage
Digital to analog conversion
Image sensors
Pixels
Electric power utilization
Data storage equipment
Digital circuits
Pulse width modulation
Capacitance
Sensors

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Yung, Y. F., & Bermak, A. (2004). A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter. In W. Badawy, & Y. Ismail (Eds.), Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004 (pp. 33-36)

A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter. / Yung, Yat Fong; Bermak, Amine.

Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004. ed. / W. Badawy; Y. Ismail. 2004. p. 33-36.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Yung, YF & Bermak, A 2004, A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter. in W Badawy & Y Ismail (eds), Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004. pp. 33-36, Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004, Banff, Alta, Canada, 19/7/04.
Yung YF, Bermak A. A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter. In Badawy W, Ismail Y, editors, Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004. 2004. p. 33-36
Yung, Yat Fong ; Bermak, Amine. / A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter. Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004. editor / W. Badawy ; Y. Ismail. 2004. pp. 33-36
@inproceedings{566ad8cb659943d092699af4f18bd1ab,
title = "A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter",
abstract = "In this paper a CMOS image sensor with on-pixel analog-to-digital convener based on PWM scheme is proposed. The digital pixel sensor includes a novel digital circuit which allows to configure the internal 8-bit memory as a 4-bit counter/memory, so as to reduce the data bit lines routed to each pixel from 8-bit to 4-bit. Hence the total parasitic capacitance as well as power consumption associated with the switching activities of the global data bus lines are reduced. Besides 8-bit precision, the imager can also be configured to 4-bit precision for low resolution applications, which has the advantage of increasing frame rate and decreasing overall power consumption. A prototype chip was realized in Alcatel 0.35μm CMOS technology. Each pixel occupies an area of 46μm × 48μm with a fill-factor of 14{\%}.",
author = "Yung, {Yat Fong} and Amine Bermak",
year = "2004",
language = "English",
isbn = "0769521827",
pages = "33--36",
editor = "W. Badawy and Y. Ismail",
booktitle = "Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004",

}

TY - GEN

T1 - A digital CMOS imager with pixel level analog-to-digital converter and reconfigurable SRAM/counter

AU - Yung, Yat Fong

AU - Bermak, Amine

PY - 2004

Y1 - 2004

N2 - In this paper a CMOS image sensor with on-pixel analog-to-digital convener based on PWM scheme is proposed. The digital pixel sensor includes a novel digital circuit which allows to configure the internal 8-bit memory as a 4-bit counter/memory, so as to reduce the data bit lines routed to each pixel from 8-bit to 4-bit. Hence the total parasitic capacitance as well as power consumption associated with the switching activities of the global data bus lines are reduced. Besides 8-bit precision, the imager can also be configured to 4-bit precision for low resolution applications, which has the advantage of increasing frame rate and decreasing overall power consumption. A prototype chip was realized in Alcatel 0.35μm CMOS technology. Each pixel occupies an area of 46μm × 48μm with a fill-factor of 14%.

AB - In this paper a CMOS image sensor with on-pixel analog-to-digital convener based on PWM scheme is proposed. The digital pixel sensor includes a novel digital circuit which allows to configure the internal 8-bit memory as a 4-bit counter/memory, so as to reduce the data bit lines routed to each pixel from 8-bit to 4-bit. Hence the total parasitic capacitance as well as power consumption associated with the switching activities of the global data bus lines are reduced. Besides 8-bit precision, the imager can also be configured to 4-bit precision for low resolution applications, which has the advantage of increasing frame rate and decreasing overall power consumption. A prototype chip was realized in Alcatel 0.35μm CMOS technology. Each pixel occupies an area of 46μm × 48μm with a fill-factor of 14%.

UR - http://www.scopus.com/inward/record.url?scp=10444226581&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=10444226581&partnerID=8YFLogxK

M3 - Conference contribution

SN - 0769521827

SP - 33

EP - 36

BT - Proceedings - 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2004

A2 - Badawy, W.

A2 - Ismail, Y.

ER -