A column-parallel inverter-based cyclic ADC for CMOS image sensor with capacitance and clock scaling

Fang Tang, Bo Wang, Amine Bermak, Xichuan Zhou, Shengdong Hu, Xiaoyong He

Research output: Contribution to journalArticle

13 Citations (Scopus)


This paper presents a low-power column-parallel inverter-based cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuit. By partially floating the capacitors inside the multiply digital-analog-converter during the least significant bit (LSB) quantization, the amplifier load capacitance could be significantly scaled down, which allows much higher settling speed and shorter cycle period. Since the signal-to-noise ratio for LSB cycle is relaxed due to the residual amplification, the proposed capacitance scaling only contributes ignorable input-referred quantization noise. Using the proposed techniques, a cyclic ADC can operate under 50% power consumption without suffering conversion rate, noise performance, and linearity. A 12-b quantization resolution test chip is fabricated using the TSMC 0.18-μm technology with 110 column-parallel ADC channels and 10.08-μm × 750-μm column pitch. The 3.5/-2 LSBs integral nonlinearity and 10.1-b effective-number-of-bit are measured under 2-μs sampling rate with 120-μW power consumption per channel.

Original languageEnglish
Article number7163317
Pages (from-to)162-167
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number1
Publication statusPublished - 1 Jan 2016
Externally publishedYes



  • CMOS image sensor
  • Column-parallel circuit
  • Cyclic analog-to-digital converter (ADC)
  • Low power
  • Mixed signal

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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