A CMOS image sensor with on-chip image compression based on predictive boundary adaptation and memoryless QTD algorithm

Shoushun Chen, Amine Bermak, Yan Wang

Research output: Contribution to journalArticle

38 Citations (Scopus)


This paper presents the architecture, algorithm, and VLSI hardware of image acquisition, storage, and compression on a single-chip CMOS image sensor. The image array is based on time domain digital pixel sensor technology equipped with nondestructive storage capability using 8-bit Static-RAM device embedded at the pixel level. The pixel-level memory is used to store the uncompressed illumination data during the integration mode as well as the compressed illumination data obtained after the compression stage. An adaptive quantization scheme based on fast boundary adaptation rule (FBAR) and differential pulse code modulation (DPCM) procedure followed by an online, least storage quadrant tree decomposition (QTD) processing is proposed enabling a robust and compact image compression processor. A prototype chip including 64 × 64 pixels, read-out and control circuitry as well as an on-chip compression processor was implemented in 0.35 μm CMOS technology with a silicon area of 3.2 × 3.0 mm2 and an overall power of 17 mW. Simulation and measurements results show compression figures corresponding to 0.6-1 bit-per-pixel (BPP), while maintaining reasonable peak signal-to-noise ratio levels.

Original languageEnglish
Article number5382495
Pages (from-to)538-547
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number4
Publication statusPublished - 1 Apr 2011



  • CMOS image sensor
  • Hilbert Scan
  • on-chip image compression
  • quadrant tree decomposition (QTD)

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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