A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic

Tarik Hammadou, Magnus Nilson, Amine Bermak, Philip Ogunbona

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

A chip architecture that integrates an optical sensor and a pixel level processing element based on binary stochastic arithmetic is proposed. The optical sensor is formed by an array of fully connected pixels, and each pixel contains a sensing element and a Pulse Frequency Modulator (PFM) converting the incident light to bit streams of identical pulses. The processing element is based on binary stochastic arithmetic to perform signal processing operations on the focal plane VLSI circuit. A 96 × 64 CMOS image sensor is fabricated using 0.5μm CMOS technology and achieves 29 × 29μm pixel size at 15% fill factor.

Original languageEnglish
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume4
Publication statusPublished - 2003
Externally publishedYes

Fingerprint

Pixels
Optical sensors
VLSI circuits
Processing
Image sensors
Modulators
Signal processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

A 96 × 64 Intelligent digital pixel array with extended binary stochastic arithmetic. / Hammadou, Tarik; Nilson, Magnus; Bermak, Amine; Ogunbona, Philip.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 4, 2003.

Research output: Contribution to journalArticle

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