A 64 fJ/step 9-bit SAR ADC array with forward error correction and mixed-signal CDS for CMOS image sensors

Denis Guangyin Chen, Fang Tang, Man Kay Law, Xiaopeng Zhong, Amine Bermak

Research output: Contribution to journalArticle

29 Citations (Scopus)

Abstract

A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper}. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additional amplifier or memory. The ADC measures 490μ{\rm m}\times 7.4μ{\rm m} and is demonstrated in a low-power CMOS image sensors with column parallel ADCs. Measurement results from the prototype image sensor in 0.18μ{\rm m} technology shows that the ADC's Differential Non-Linearity (DNL) is reduced from 3.5 LSB to 1.2 LSB by its mixed-signal FEC algorithm, making its Figure-of-Merit (FoM) 64 fJ/step. Furthermore, when combined with the ADC's mixed-signal Correlated-Double-Sampling, the column FPN is reduced from 3.2% to 0.5% without any additional circuit.

Original languageEnglish
Article number6858095
Pages (from-to)3085-3093
Number of pages9
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume61
Issue number11
DOIs
Publication statusPublished - 1 Nov 2014
Externally publishedYes

Fingerprint

Forward error correction
Image sensors
Sampling
Digital to analog conversion
Capacitors
Data storage equipment
Networks (circuits)

Keywords

  • CMOS image sensor (CIS)
  • column-parallel SAR ADC
  • correlated double sampling (CDS)
  • error correction
  • single-ended ADC

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 64 fJ/step 9-bit SAR ADC array with forward error correction and mixed-signal CDS for CMOS image sensors. / Chen, Denis Guangyin; Tang, Fang; Law, Man Kay; Zhong, Xiaopeng; Bermak, Amine.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 61, No. 11, 6858095, 01.11.2014, p. 3085-3093.

Research output: Contribution to journalArticle

@article{59d9e1ad5c09435fa4e02d6fb0ca64a4,
title = "A 64 fJ/step 9-bit SAR ADC array with forward error correction and mixed-signal CDS for CMOS image sensors",
abstract = "A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper}. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additional amplifier or memory. The ADC measures 490μ{\rm m}\times 7.4μ{\rm m} and is demonstrated in a low-power CMOS image sensors with column parallel ADCs. Measurement results from the prototype image sensor in 0.18μ{\rm m} technology shows that the ADC's Differential Non-Linearity (DNL) is reduced from 3.5 LSB to 1.2 LSB by its mixed-signal FEC algorithm, making its Figure-of-Merit (FoM) 64 fJ/step. Furthermore, when combined with the ADC's mixed-signal Correlated-Double-Sampling, the column FPN is reduced from 3.2{\%} to 0.5{\%} without any additional circuit.",
keywords = "CMOS image sensor (CIS), column-parallel SAR ADC, correlated double sampling (CDS), error correction, single-ended ADC",
author = "Chen, {Denis Guangyin} and Fang Tang and Law, {Man Kay} and Xiaopeng Zhong and Amine Bermak",
year = "2014",
month = "11",
day = "1",
doi = "10.1109/TCSI.2014.2334852",
language = "English",
volume = "61",
pages = "3085--3093",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "11",

}

TY - JOUR

T1 - A 64 fJ/step 9-bit SAR ADC array with forward error correction and mixed-signal CDS for CMOS image sensors

AU - Chen, Denis Guangyin

AU - Tang, Fang

AU - Law, Man Kay

AU - Zhong, Xiaopeng

AU - Bermak, Amine

PY - 2014/11/1

Y1 - 2014/11/1

N2 - A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper}. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additional amplifier or memory. The ADC measures 490μ{\rm m}\times 7.4μ{\rm m} and is demonstrated in a low-power CMOS image sensors with column parallel ADCs. Measurement results from the prototype image sensor in 0.18μ{\rm m} technology shows that the ADC's Differential Non-Linearity (DNL) is reduced from 3.5 LSB to 1.2 LSB by its mixed-signal FEC algorithm, making its Figure-of-Merit (FoM) 64 fJ/step. Furthermore, when combined with the ADC's mixed-signal Correlated-Double-Sampling, the column FPN is reduced from 3.2% to 0.5% without any additional circuit.

AB - A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper}. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additional amplifier or memory. The ADC measures 490μ{\rm m}\times 7.4μ{\rm m} and is demonstrated in a low-power CMOS image sensors with column parallel ADCs. Measurement results from the prototype image sensor in 0.18μ{\rm m} technology shows that the ADC's Differential Non-Linearity (DNL) is reduced from 3.5 LSB to 1.2 LSB by its mixed-signal FEC algorithm, making its Figure-of-Merit (FoM) 64 fJ/step. Furthermore, when combined with the ADC's mixed-signal Correlated-Double-Sampling, the column FPN is reduced from 3.2% to 0.5% without any additional circuit.

KW - CMOS image sensor (CIS)

KW - column-parallel SAR ADC

KW - correlated double sampling (CDS)

KW - error correction

KW - single-ended ADC

UR - http://www.scopus.com/inward/record.url?scp=84908451422&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84908451422&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2014.2334852

DO - 10.1109/TCSI.2014.2334852

M3 - Article

AN - SCOPUS:84908451422

VL - 61

SP - 3085

EP - 3093

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1549-8328

IS - 11

M1 - 6858095

ER -