A 64 × 64 CMOS digital pixel array based on pulse width analogue to digital conversion, with on chip linearising circuit

Alistair J. Kitchen, Amine Bermak, Abdessalam Bouzerdoum

Research output: Contribution to journalArticle

Abstract

This paper describes a 64 × 64 digital pixel array employing a pulse width analogue to digital conversion scheme. Each pixel contains a photodiode sensor, comparator and memory, and in conjunction with a central control circuit performs the analogue to digital conversion, by timing a pulse generated by the photodiode/comparator circuit. The control circuit produces data which compensates for this nonlinear relationship, resulting in a pixel parallel ADC operation. The digital image data can be read from the array non-destructively, with random access. The array is constructed in a standard 0.35μm, 3.3 V digital CMOS process.

Original languageEnglish
Pages (from-to)163-171
Number of pages9
JournalProceedings of SPIE - The International Society for Optical Engineering
Volume5274
DOIs
Publication statusPublished - 2004
Externally publishedYes

Fingerprint

Analog to digital conversion
CMOS
pulse duration
Chip
Pixel
Pixels
pixels
chips
analogs
Photodiodes
Analogue
photodiodes
Networks (circuits)
Photodiode
comparator circuits
Comparator circuits
random access
Random Access
Digital Image
time measurement

Keywords

  • CMOS pixel
  • DPS
  • Pixel

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics

Cite this

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