A 2.2μW 15b incremental delta-sigma ADC with output-driven input segmentation

Bo Wang, Man Kay Law, Saqib Mohamad, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

A micro-power incremental delta-sigma (I-ΣS) ADC is presented. This ADC uses its decimation filter's output to estimate the input signal level and dynamically adjusts the modulator feedback voltage, thereby reducing the integrator input range and power. For further power saving, integrator time-multiplexing is also employed. Fabricated in 0.18μm CMOS, the 0.12mm2 ADC consumes 2.16μW at a conversion speed of 85S/s, 15.3b resolution and-2/1.5LSB INL.

Original languageEnglish
Title of host publication2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages7-8
Number of pages2
Volume25-28-January-2016
ISBN (Electronic)9781467395694
DOIs
Publication statusPublished - 7 Mar 2016
Event21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 - Macao, Macao
Duration: 25 Jan 201628 Jan 2016

Other

Other21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016
CountryMacao
CityMacao
Period25/1/1628/1/16

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Keywords

  • dual-feedback ΣS modulator
  • incremental delta-sigma ADC
  • integrator multiplexing
  • low power ADC

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design

Cite this

Wang, B., Law, M. K., Mohamad, S., & Bermak, A. (2016). A 2.2μW 15b incremental delta-sigma ADC with output-driven input segmentation. In 2016 21st Asia and South Pacific Design Automation Conference, ASP-DAC 2016 (Vol. 25-28-January-2016, pp. 7-8). [7427975] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2016.7427975