A 14-bit 70MS/s pipeline ADC with power-efficient back-end stages

Moaaz Ahmed, Fang Tang, Amine Bermak

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

A 14-bit SHA-less pipeline ADC based on 2.5-bit per stage architecture is proposed. Implemented in TSMC 0.18μm CMOS process, the proposed ADC achieves an ENOB of 11.34-bits and consumes 41 mW power at 70 MS/s thereby achieving an FOM of 226fJ/conversion-step which compares favorably with state-of-the-art work. The low-power consumption is attributed to the careful design of back-end stages based on a novel gain-boosting recycling folded-cascode amplifier.

Original languageEnglish
Title of host publicationProceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages154-157
Number of pages4
ISBN (Electronic)9781479983636
DOIs
Publication statusPublished - 30 Sep 2015
Externally publishedYes
Event11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 - Singapore, Singapore
Duration: 1 Jun 20154 Jun 2015

Other

Other11th IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015
CountrySingapore
CitySingapore
Period1/6/154/6/15

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Keywords

  • Gain boosting
  • Recycling folded cascode amplifier
  • SHA-less pipeline ADC

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Ahmed, M., Tang, F., & Bermak, A. (2015). A 14-bit 70MS/s pipeline ADC with power-efficient back-end stages. In Proceedings of the 2015 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2015 (pp. 154-157). [7285073] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2015.7285073