A 124 fJ/Bit cascode current mirror array based PUF with 1.50% native unstable bit ratio

Xiaojin Zhao, Peizhou Gan, Qiang Zhao, Dejian Liang, Yuan Cao, Xiaofang Pan, Amine Bermak

Research output: Contribution to journalArticle

Abstract

In this paper, we present a novel physical unclonable function (PUF) design based on cascode current mirror array. By using a single-stage cascode amplifier for each PUF cell, the output impedance can be significantly elevated. Compared with a traditional single-stage amplifier-based current-mode PUF, the proposed structure is capable of generating more polarized voltage value for the output node. With an additional digital buffer, the temporal noise can be well-suppressed, and a rail-to-rail digital output can be provided with high native reliability. Moreover, through operating the transistors at the subthreshold region, the overall power consumption can be dramatically reduced. Featuring a compact footprint of 3.23μm2 (i.e. 764 F2) for each PUF cell, the proposed PUF implementation is validated using 65-nm standard CMOS process. The excellent randomness of the proposed PUF design is verified based on the test results with widely-accepted auto-correlation function and NIST suites. Meanwhile, the PUF's uniqueness is measured with 10 chip prototypes and reported to be 49.94%. In addition, the fabricated PUF chips were also characterized with various environmental influences. With multiple readout (500 times) under the reference operating temperature of 27 °C and supply voltage of 1.2 V, the native unstable bit ratio is measured to be as low as 1.50%, which can be further improved to 0.79% by adopting the mainstream temporal majority voting (TMV)-based error correction scheme. Besides, we also evaluate the fabricated PUF chips' reliability under varied operating temperature from -40 °C to 120 °C and supply voltage from 0.95 to 1.3 V. The averaged bit error rate (BER) per 10 °C and BER per 0.1 V are measured to be 0.86% and 1.02%, respectively. Compared with the state-of-the-art implementations, the reliability figure of merit (RFoM) is improved by 1.16∼ 4.29×, with the influences of the temporal noise, the temperature/supply voltage variations and their ranges comprehensively considered.

Original languageEnglish
Article number8770256
Pages (from-to)3494-3503
Number of pages10
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume66
Issue number9
DOIs
Publication statusPublished - 1 Sep 2019

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Mirrors
Electric potential
Bit error rate
Rails
Hardware security
Error correction
Autocorrelation
Temperature
Transistors
Electric power utilization

Keywords

  • cascode current mirror
  • high reliability
  • low power consumption
  • Physical unclonable function

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A 124 fJ/Bit cascode current mirror array based PUF with 1.50% native unstable bit ratio. / Zhao, Xiaojin; Gan, Peizhou; Zhao, Qiang; Liang, Dejian; Cao, Yuan; Pan, Xiaofang; Bermak, Amine.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, No. 9, 8770256, 01.09.2019, p. 3494-3503.

Research output: Contribution to journalArticle

Zhao, Xiaojin ; Gan, Peizhou ; Zhao, Qiang ; Liang, Dejian ; Cao, Yuan ; Pan, Xiaofang ; Bermak, Amine. / A 124 fJ/Bit cascode current mirror array based PUF with 1.50% native unstable bit ratio. In: IEEE Transactions on Circuits and Systems I: Regular Papers. 2019 ; Vol. 66, No. 9. pp. 3494-3503.
@article{18776aacf0284d14bd6650f724c77799,
title = "A 124 fJ/Bit cascode current mirror array based PUF with 1.50{\%} native unstable bit ratio",
abstract = "In this paper, we present a novel physical unclonable function (PUF) design based on cascode current mirror array. By using a single-stage cascode amplifier for each PUF cell, the output impedance can be significantly elevated. Compared with a traditional single-stage amplifier-based current-mode PUF, the proposed structure is capable of generating more polarized voltage value for the output node. With an additional digital buffer, the temporal noise can be well-suppressed, and a rail-to-rail digital output can be provided with high native reliability. Moreover, through operating the transistors at the subthreshold region, the overall power consumption can be dramatically reduced. Featuring a compact footprint of 3.23μm2 (i.e. 764 F2) for each PUF cell, the proposed PUF implementation is validated using 65-nm standard CMOS process. The excellent randomness of the proposed PUF design is verified based on the test results with widely-accepted auto-correlation function and NIST suites. Meanwhile, the PUF's uniqueness is measured with 10 chip prototypes and reported to be 49.94{\%}. In addition, the fabricated PUF chips were also characterized with various environmental influences. With multiple readout (500 times) under the reference operating temperature of 27 °C and supply voltage of 1.2 V, the native unstable bit ratio is measured to be as low as 1.50{\%}, which can be further improved to 0.79{\%} by adopting the mainstream temporal majority voting (TMV)-based error correction scheme. Besides, we also evaluate the fabricated PUF chips' reliability under varied operating temperature from -40 °C to 120 °C and supply voltage from 0.95 to 1.3 V. The averaged bit error rate (BER) per 10 °C and BER per 0.1 V are measured to be 0.86{\%} and 1.02{\%}, respectively. Compared with the state-of-the-art implementations, the reliability figure of merit (RFoM) is improved by 1.16∼ 4.29×, with the influences of the temporal noise, the temperature/supply voltage variations and their ranges comprehensively considered.",
keywords = "cascode current mirror, high reliability, low power consumption, Physical unclonable function",
author = "Xiaojin Zhao and Peizhou Gan and Qiang Zhao and Dejian Liang and Yuan Cao and Xiaofang Pan and Amine Bermak",
year = "2019",
month = "9",
day = "1",
doi = "10.1109/TCSI.2019.2927758",
language = "English",
volume = "66",
pages = "3494--3503",
journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",
issn = "1549-8328",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "9",

}

TY - JOUR

T1 - A 124 fJ/Bit cascode current mirror array based PUF with 1.50% native unstable bit ratio

AU - Zhao, Xiaojin

AU - Gan, Peizhou

AU - Zhao, Qiang

AU - Liang, Dejian

AU - Cao, Yuan

AU - Pan, Xiaofang

AU - Bermak, Amine

PY - 2019/9/1

Y1 - 2019/9/1

N2 - In this paper, we present a novel physical unclonable function (PUF) design based on cascode current mirror array. By using a single-stage cascode amplifier for each PUF cell, the output impedance can be significantly elevated. Compared with a traditional single-stage amplifier-based current-mode PUF, the proposed structure is capable of generating more polarized voltage value for the output node. With an additional digital buffer, the temporal noise can be well-suppressed, and a rail-to-rail digital output can be provided with high native reliability. Moreover, through operating the transistors at the subthreshold region, the overall power consumption can be dramatically reduced. Featuring a compact footprint of 3.23μm2 (i.e. 764 F2) for each PUF cell, the proposed PUF implementation is validated using 65-nm standard CMOS process. The excellent randomness of the proposed PUF design is verified based on the test results with widely-accepted auto-correlation function and NIST suites. Meanwhile, the PUF's uniqueness is measured with 10 chip prototypes and reported to be 49.94%. In addition, the fabricated PUF chips were also characterized with various environmental influences. With multiple readout (500 times) under the reference operating temperature of 27 °C and supply voltage of 1.2 V, the native unstable bit ratio is measured to be as low as 1.50%, which can be further improved to 0.79% by adopting the mainstream temporal majority voting (TMV)-based error correction scheme. Besides, we also evaluate the fabricated PUF chips' reliability under varied operating temperature from -40 °C to 120 °C and supply voltage from 0.95 to 1.3 V. The averaged bit error rate (BER) per 10 °C and BER per 0.1 V are measured to be 0.86% and 1.02%, respectively. Compared with the state-of-the-art implementations, the reliability figure of merit (RFoM) is improved by 1.16∼ 4.29×, with the influences of the temporal noise, the temperature/supply voltage variations and their ranges comprehensively considered.

AB - In this paper, we present a novel physical unclonable function (PUF) design based on cascode current mirror array. By using a single-stage cascode amplifier for each PUF cell, the output impedance can be significantly elevated. Compared with a traditional single-stage amplifier-based current-mode PUF, the proposed structure is capable of generating more polarized voltage value for the output node. With an additional digital buffer, the temporal noise can be well-suppressed, and a rail-to-rail digital output can be provided with high native reliability. Moreover, through operating the transistors at the subthreshold region, the overall power consumption can be dramatically reduced. Featuring a compact footprint of 3.23μm2 (i.e. 764 F2) for each PUF cell, the proposed PUF implementation is validated using 65-nm standard CMOS process. The excellent randomness of the proposed PUF design is verified based on the test results with widely-accepted auto-correlation function and NIST suites. Meanwhile, the PUF's uniqueness is measured with 10 chip prototypes and reported to be 49.94%. In addition, the fabricated PUF chips were also characterized with various environmental influences. With multiple readout (500 times) under the reference operating temperature of 27 °C and supply voltage of 1.2 V, the native unstable bit ratio is measured to be as low as 1.50%, which can be further improved to 0.79% by adopting the mainstream temporal majority voting (TMV)-based error correction scheme. Besides, we also evaluate the fabricated PUF chips' reliability under varied operating temperature from -40 °C to 120 °C and supply voltage from 0.95 to 1.3 V. The averaged bit error rate (BER) per 10 °C and BER per 0.1 V are measured to be 0.86% and 1.02%, respectively. Compared with the state-of-the-art implementations, the reliability figure of merit (RFoM) is improved by 1.16∼ 4.29×, with the influences of the temporal noise, the temperature/supply voltage variations and their ranges comprehensively considered.

KW - cascode current mirror

KW - high reliability

KW - low power consumption

KW - Physical unclonable function

UR - http://www.scopus.com/inward/record.url?scp=85071952500&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85071952500&partnerID=8YFLogxK

U2 - 10.1109/TCSI.2019.2927758

DO - 10.1109/TCSI.2019.2927758

M3 - Article

VL - 66

SP - 3494

EP - 3503

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1549-8328

IS - 9

M1 - 8770256

ER -