3D packaging technology for vision CMOS VLSI

Review and performance evaluation

Amine Bermak, A. Bouzerdoum, K. Eshraghian

Research output: Contribution to journalArticle

Abstract

In many applications, such as multimedia and on-chip camera, there is a need for the production of low power, low weight and low cost integrated circuits. Several CMOS vision chips have been proposed in the literature. Some limitations of conventional 2D architectures are discussed and a new 3D generation of vision chips is presented and reviewed in this paper. As a result of this analysis, some conclusions on the advantages and limitations of 2D vision chips and the feasibility of the 3D approach are explored.

Original languageEnglish
Pages (from-to)248-256
Number of pages9
JournalProceedings of SPIE - The International Society for Optical Engineering
Volume3891
Publication statusPublished - 1999
Externally publishedYes

Fingerprint

Packaging
very large scale integration
packaging
Integrated circuits
Performance Evaluation
CMOS
Chip
Cameras
chips
evaluation
Costs
low weight
multimedia
Integrated Circuits
integrated circuits
Multimedia
Camera
cameras
costs
Vision

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Condensed Matter Physics

Cite this

3D packaging technology for vision CMOS VLSI : Review and performance evaluation. / Bermak, Amine; Bouzerdoum, A.; Eshraghian, K.

In: Proceedings of SPIE - The International Society for Optical Engineering, Vol. 3891, 1999, p. 248-256.

Research output: Contribution to journalArticle

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